Compute values of main signal and country signal state changes only at positive edge of clock if TRUE, indicates that there is car on Module sig_control (hwy, cntry, X, clock, clear) Is there something I am missing when using Icarus such as I must manually set the start time to 0 for an accurate result later in the simulation, or Silos auto-initializes variables which I must do manually in Icarus? This code is taken form a Verilog HDL book which can be found here Also, when changing the repeat R2GDELAY to 3, Icarus also does not seem to preform as expected. The Silos repeat function works as I would expect, but when using Icarus I can't really seem to figure out how they got that result. If I simulate it in Icarus (iverlog and vvp) the time differs from Silos(the starting at 0 rather than 200 I don't care about as much as Silos has 235 -> 255 and Icarus has 235 -> 265). If I simulate it in Silos, the code functions as expected. I am recieving some strange results when trying to compile and simulate a Verilog module and stimulus.
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